Intel's 18A-P Debuts Power Boost, an Industry-First Dual-Contact Transistor That Squeezes More Frequency From the Same Chip Footprint

Intel unveiled full details of its 18A-P process technology at VLSI 2026 on June 16, debuting an industry-first dual-contact transistor architecture called Power Boost that delivers 9% higher performance at the same power or 18% lower power at the same performance compared to its existing 18A node. The announcement represents Intel's most significant foundry advancement in years and a credible challenge to TSMC's dominance in advanced semiconductor manufacturing.

**What 18A-P Actually Does**

Intel's 18A-P builds on the same gate-all-around (GAA) RibbonFET and backside power delivery (PowerVia) foundation as 18A, but introduces several critical innovations. The headline feature is Power Boost — the industry's first implementation of a dual-contact architecture for both NMOS and PMOS transistors, enabled by backside power delivery.

In conventional transistor designs, electrical contacts are made only from the top of the chip. Power Boost adds a second contact from the backside of the wafer through Intel's PowerVia technology, effectively creating two pathways for current to flow through each transistor. The result: increased drive current and higher frequency at matched capacitance — meaning chips can run faster without using more power or generating more heat.

This is not incremental. Dual-contact architecture has been theorized for years but never manufactured at scale. Intel's ability to pull it off in a production-ready node (18A-P is now in risk production) signals that its foundry technology may have turned a corner after years of falling behind TSMC and Samsung.

**Beyond Power Boost: The Full Feature Set**

Intel didn't stop at dual contacts. 18A-P includes a suite of improvements designed to make the node attractive to both internal and external foundry customers:

- **20-40% improved thermal resistance** through materials and design innovations — critical for high-power AI and HPC chips that generate massive heat - **10-30% improved via resistance** (vertical connections between chip layers) through geometric and materials optimizations - **PMOS mobility enhancement** via strain engineering, allowing current to move through transistors more efficiently - **A new fifth logic Vt pair** between ultra-low voltage and low voltage thresholds, giving chip designers more options to balance speed and power consumption - **Full design rule compatibility with 18A**, enabling straightforward reuse of existing IP and design flows — this is a big deal for customers who don't want to redesign their chips from scratch

The compatibility point deserves emphasis. TSMC's node transitions often require significant redesigns. Intel is betting that backward compatibility will make 18A-P an easier adoption decision for companies already designing on 18A.

**The Foundry Stakes**

Intel's foundry business has been the subject of intense scrutiny. After years of process delays and lost market share, the company's 18A node showed genuine progress, and 18A-P appears to build on that momentum. At Computex 2026, Intel officially announced Diamond Rapids, its next-generation Xeon server CPUs, will be built on 18A-P — a signal that the company trusts the node enough for its own flagship products.

External customer traction is also growing. Reports indicate that TeraFab, SpaceX, and Apple are among the early foundry customers, with NVIDIA and Google expected to follow. If these partnerships materialize at scale, Intel's foundry could become a meaningful alternative to TSMC for advanced nodes — something the industry desperately needs as AI chip demand continues to outstrip supply.

**The Research Pipeline**

Intel also used VLSI 2026 to showcase longer-term research that could shape the next decade of semiconductor manufacturing:

- **Hybrid GaN and silicon logic**: Working with UC San Diego, Intel demonstrated efficient digital control circuits using gallium nitride nMOS and silicon pMOS on a single 300mm chip — achieving a record power-delay product of 6.2 attojoules per stage, over 1,000x more efficient than previous GaN logic approaches. This could eventually enable on-chip power management at dramatically lower cost and complexity.

- **CFET integration at 45nm gate pitch**: Intel built working logic circuits using complementary FET 3D transistors — stacking NMOS and PMOS vertically for more performance in less space — at an extremely small 45nm pitch, with backside power delivery and novel interconnect features. CFETs are widely considered the successor to GAA transistors for sub-1nm nodes.

- **Subtractive Ru interconnects with airgap**: Intel demonstrated a next-generation wiring approach using ruthenium with airgaps, achieving up to 35% capacitance reduction and roughly 2% circuit performance improvement over conventional copper interconnects — a scalable path for improving signal transmission at tight pitches.

**What This Means For You**

If you follow the semiconductor industry, Intel's 18A-P announcement is a genuine positive signal. The company has been promising a foundry turnaround for years; 18A-P with Power Boost is the strongest evidence yet that the turnaround is real. Dual-contact transistors at risk production is not a slide deck — it's silicon.

For the broader tech industry, Intel's foundry resurgence matters because it would end TSMC's near-monopoly on advanced chip manufacturing. That would reduce supply chain risk, lower costs through competition, and potentially accelerate the AI infrastructure buildout by removing a key bottleneck.

For investors, the question is execution. 18A-P in risk production is not the same as 18A-P in high-volume manufacturing. Intel needs to deliver working chips at scale, on time, and at competitive yields. If Diamond Rapids ships on 18A-P without delays, and if external customers like Apple and NVIDIA follow through, Intel's foundry business could be worth multiples of its current valuation. If history repeats and delays mount, 18A-P will be remembered as another promising Intel node that couldn't escape the fab.